In the patent referenced above there is disclosed a circuit for performing multiplication modulo N, where N is preferably a large prime number. Such circuits are useful for carrying out exponentiation operations modulo N. Such mathematical operations lie at the heart of a significant number of methods for encrypting and for decrypting data. The circuits disclosed provide a powerful and flexible method for such processing using concatenated arrays of what are referred to therein as “processing elements.” The similarity in structure of these processing elements is also seen to be of value in structuring a process in which operations are pipelined, thus increasing overall throughput. Accordingly, it is seen that the referenced issued patent provides a useful cryptographic engine which is used in the present invention.
It is also seen that the above referenced published patent application discloses a secure processing chip which includes: a cryptographic engine such as the one in the above-mentioned issued patent, a microprocessor, an internal memory, and a hybrid FPGA/ASIC (Application Specific Integrated Circuit) chip controller. This controller provides a secure mechanism along with internal hardwired cryptographic key structures, such as fuses, which are used in decoding instruction streams which are passed to chip internals as a method for providing secure programming and structure for the FPGA/ASIC chip controller. In their normal operation subsequent to secure programming operations, these processing chips (COACH devices) receive strings of instructions through an I/O interface in the form of request blocks which may or may not be encrypted.
These chips are useable in groups without impacting their secure nature. An array of these groups is employed in the present invention. This structure provides a more flexible system which is capable of cryptographic processing in which the length of the keys is employable as a selector of the number of COACH chips to be employed in a given encryption or decryption operation or string of operations.